This invention relates to a bilinear integrator circuit for sampled signal currents.
The invention provides a bilinear integrator circuit for sampled signal currents comprising first and second inputs and an output, means for connecting the first input to the input of a first current memory cell which is arranged to store the current applied in a first portion of each sampling period and to reproduce a current, whose magnitude is dependent on that of the applied current, at an output during a second portion of that or a succeeding sample period, means for connecting the second input to the input of a second current memory bell which is arranged to store the current applied to its input in the second portion of each sampling period and to reproduce at each of a plurality of outputs a current, whose magnitude is dependent upon that of the current applied to its input, during the first portion of that or a succeeding sampling period, means for connecting the first output of the second current memory cell to the input of the first current memory cell, means for connecting the output of the first current memory cell to the input of the second current memory cell, and means for connecting the second output of the second current memory cell to the output of the integrator circuit.
UK Patent Application No. 8721758 (equivalent U.S. Pat. No. 4,864,217) discloses a method of processing sampled analogue electrical signals comprising the steps of
a) converting each sample into a current if it is not already in that form;
b) combining, in predetermined proportions, the input sample current in a present sample period with the sample current(s) derived from input sample current(s) in one or more preceding sample periods; and
c) deriving the processed output signal from the combined current produced by step b) in successive sampling periods.